Logarithmic converters



Aug 2 1966 G. a. PARKINSQN LOG'ARITHMIC CONVERTERS Filed, May :51,A 196s 3 Sheets-Sheet 1 R. m m V W GEOFFREY B. PARKlNsoN mlm AGENT |2265 @Olzd Aug. 2, 1966 G. B. PARKINSON LOGAR IIHMI C CONVERTERS 3 Sheets-Sheva 2 Filed Maly 51, 1965 All . .DaPDO NVENTOR. GEOFFREY B. PARK INSON AGENT s 5 Sheets-Sheet CS AGFNT Aug' 2 E966 G. E. PARKINSGN LOGRI'IHMIC` CONVERTERS Filed May 31, 1963 3,264,637 LOGARITHMIC CONVERTERS Geotrey B. Parkinson, Waltham, Mass., assignor to Raytheon Company, Lexington, Mass., a corporation ol Delaware Filed May 31, 1963, Ser. No. 284,483 7 Claims. (Cl. 340-347) The present invention relates to conye'rter systems and more particularly to encoding systems for effecting the conversion of analog signals to provide a digital logarithmic representation of said analog signals. Additionally, this invention relates to a converter system for effecting conversion of a logarithmic digital signal to obtain an analog signal representative of said logarithmic digi-tal signal.

Various means have heretofore been proposed in the prior art for converting analog information to digital information and vice versa. IPrior art logarithmic conversion systems generally relate to mechanical devices such as, for example, cathode ray lraster techniques to provide a logarithmic digital signal representative of an analog input. Additionally, mechanically rotated encoded disks have been provided which operate on an analog signal to provide a digital representation in logarithmic form of said analog signal.

Other prior art systems have disclosed the use of an analog device for providing a logarithmic analog signal representative of an analog input signal in combination with a linear or other type of analog to digital converter, thereby obtaining a digital signal representative of the logarithmic analog input signal. This above-mentioned type of device using the combination of a logarithmic analog device and linear analog to digital converter has required an undesirable complexity of equipment to provide this logarithmic digital output.

Accordingly, it is an object of this invention to provide a new, useful and improved converter lfor effecting the conversion of an analog signal to a digital signal without the requirement of a logarithmic analog device in combination `with an analog to digital device.

It is a further object of this invention to provide an improved electrical device for convert-ing an analog signal varying over a wide dynamic range to its logarithmic digital representation.

It is an additional object of this invention to quantize an analog signal in accordance with feedback principles to provide a logarithmic digital representation of said analog signal.

A further object of this invention is to provide an antilogarithmic device which converts a logarithm-ic digital signal to obtain an analog signal representative of Said logarithmic digital signal.

In accordance Iwith this invention, electrical means for convert-ing an analog signal or voltage to a logarithmic digital signal including means for obtaining the product of a signal and a factor is provided without the requirement of a separate analog to logarithmic analog conversion device in combination with an analog to digital conversion device. In the preferred embodiment of this invention, an analog signal input voltage to bek converted is applied to a voltage comparator device where it is compared with a comparison signal. The antilogarithmic digital to analog conversion dev-ice for providing this voltage comparison signal operates utilizing feedback encoding techniques wherein a logically controlled register or storage device provides signals for selectively and sequentially operating and stepping a plurality of switches of said digital to analog conversion device. This technique permits a reference signal to be selectively multiplied by either a constant or a factor F which is the base of the desired logarithmic to a power,

Patented August: 2, 1966 thereby obtaining a comparison signal substantially equal in magnitude to the analog signal. The digital register is then sampled after the comparison process is completed to obtain a digital signal representative of the logarithmic of the analog signal.

The above-mentioned and other features and objects of this invention and the manner of obtaining them will best be understood by reference to the following description of an embodiment of the invention taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a particular system for producing a Ibinary code representative of the logarithm to any particular base of a given analog signal;

FIG, 2 illustrates the details of the anti-logarithmic digital to analog converter of FIG. 1;

FIG. .3 shows a logical flow diagram of the timing and control circuit of FIG. 1;

FIG. 4 shows a typical delay line section in schematic form; and

FIG. 5 is a schematic diagram of a typical pulse amplier for use in the timing and control circuits of FIG. 3.

Although the principle of operation of the present invention is applicable to any number of bits to provide a digital output number representative of the logarithm of an analog signal to any desired ylogarithmic base, apparatus supplying six bits to represent a number 7.875 is considered sufficient for illustrative purposes and will be described herein by way of example.

In FIG. 1 an input analog signal or voltage the amplitude of which contains information, such as that which could be obtainable in the monitoring of chemical or other types of processes, is applied to a voltage sampler or comparator 13 wherein it is compared with a co'mparison signal or voltage EC in order to determine whether or not the input analog voltage EA is greater or less than the comparison voltage. The voltage comparator 13 could be of the type found in chapter 15 of the book Puls-e and Digital Circuits by Millman and Taub, published by the McGraw Hill Book Company in 1956 and more particularly could be the difference amplifier shown on page 467 of this book.

The output signal from the voltage comparator 13 is provided to a timing and control circuit 10 for providing a plurality of logical signals from its output lines a, b, c, d, e, f, g, l1, i, i, k and l to control a digital output register 11. The timing and control circuit 10 is shown in FIG. 3 and operation will be discussed in conjunction With a description of FIG. 3. The digital output register l1 operates to selectively provide a plurality of signals to actuate an anti-logarithmic digital to analog converter which is used to generate the aforementioned comparison signal Ec. Additionally, at the completion of the comparison the digital output register 11 can be sampled utilizing standard digital techniques in order to obtain a logarithmic digital output representative of the analog input signal. The digital output register 11 comprises six bi-stiable flip-flops referred to as bi-stable ip-op A, shown as 20, bi-stable ilipilop B, shown as 30, bi-stable flip-Hop C, shown as 40, bi-stable Hip-Hop D, shown as 50, bi-stable flip-flop E, shown as 6i) and bi-stable fiip-op F, shown as 70. Each of these flip-flops is shown having its 4l output coupled to a plurality of switches in the logarithmic digital to analog converter 12 to provide control signals to said switches in accordance with control signals from the timing and control circuit 1l). The bistable tiip-llops could be of the type shown in chapter 5 of the book Pulse and Digital Circuits referred to above in conjunction with the voltage comparator and, more particularly, could be the circuit shown on page 142 ot the above-referenced book.

rIlhe aforementioned anti-logarithmic digital to analog converter 12 is shown for providing a comparison voltage Ec by selectively multiplying a reference signal or voltage Eo by a plurality of multiplication factors in accordance with signals provided by said digital register 1l. For purposes of explanation, the anti-logarithmic digital to analog converter 12 will rst be described with relation .to the block diagram of FlG. 1, and will be further described after completion of this description with reference to the schematic diagram of FIG. 2 in order to set forth a particular circuit which is capable of operating as an anti-logarithmic digital to analog converter. Referring to FIG. 1, the anti-logarithmic digital to analog converter 12 comprises a plurality of two position switches, such as switch A, 23, having contacts 24 and 25 with an arm 26 able to be closed on either contact 24 or 25. Switch 23, which is shown coupled to bi-stable flip-flop A, has its arm 26 positioned on contact 25 in the absence of a signal lor voltage on the l line from bi-stable flip-hop A and has its arm 26 positioned on Contact 24 in the presence of a signal or voltage on the l line of bi-stable flip-flop A. While switch A cornprises a relay as shown in FIG. 2, other embodiments could utilize electronic switches comprising diode or transistor networks. Shown coupled to switch A at contacts 24 and 25 .are two multiplication factor devices shown as blocks 21 and 22. Devices for providing multiplication factors could comprise the operational amplifier circuit shown in FIG. 2, or alternatively could be constructed utilizing resistive attenuation networks and other types of operational amplier circuits known to the analog computer art. Block 21 represents a device for multiplying a signal by [14, wherein a" represents the base of the required logarithm.. Block 22 is shown for multiplying a signal such as Eo times 1. Depending upon the position of arm 26 of switch A, a signal such as Eo will be multiplied by either a or 1 and thus the comparison signal Ec, which is equal to Eo times a factor, will be a function of the position of the arm 26 of switch A.

There is also shown a switch B, 33, functioning the same as switch A and having contacts 34 and 35 and a moving arm 36 which is positioned either at contact 34 or 35 in accordance with an output from bi-stable ipop B. Coupled to switch B are two blocks 31 and 32 representing the multiplication factors l and (12. These blocks 31 and 32 affect t'he input reference voltage E in the same manner as described with relation to blocks 21 and 22, thus affecting the magnitude of the generated comparison voltage Ec. A third switch C, 43, is also shown having contacts 44 and 45 with an arm 46 responsive to an output signal from bi-stableillip-flop C. A block 41 is shown for providing a multiplication factor a in one path and a multiplication factor "1 in another path. This device functions similarly as described with relation to blocks 31 and 32 and affects the magnitude of the comparison voltage Ec depending upon the position of arm 46. Further, a switch E, 53, having contacts 54 and 55 with a movable arm 56, responsive to the presence of an output signal from bi-stable Hip-flop D, is shown having connected to it a block 51 providing a multiplication factor a"' in one path and a multiplication factor of l in another path. Switch D in blocks 51 and 52 operates in the same manner as described with relation to blocks 41 and 42 in switch C above, and accordingly affect the magnitude of the comparison signal Ec.

A iftth switch E, 63, is shown having contacts 64 and 65 and a movable arm 66, which is responsive to an output signal provided from bi-stable flip-flop E. Block 61 is shown in one signal path coupled to switch E for providing a multiplication factor aV-f and a block 62 is shown for providing a multiplication factor l in another signal path. Switch E and blocks 61 and 62 perform in the same manner as described with relation to switch D and blocks S1 and 52 mentioned above, and therefore,

i accordingly aticct the magnitude of the comparison signal lic.

The sixth switch F, 73, having contacts 74 and 75 with a movable arm 76 responds to an output signal from hi-stable flip-flop F. In one signal path there is shown a block 71 for providing a multiplication factor ah and a block 72 in another signal path for providing a multiplication factor 1. Blocks 71 and 72 are shown `coupled to a reference voltage Eo. Switch F and blocks 71 and 72 operate similarly as described with reference to blocks 61 and 62 and switch E above, and thus, accordinglyaffect the magnitude of the comparison voltage Ec. From this it can thus be seen that if a reference voltage 13o is applied to the logarithmic digital to analog converter 12, f

a comparison voltage EC is generated which is a function of the position of the arms 26, 36, 46, 56, 66 and 76 of switches A, B, C, D, E and F, respectively, of converter 12. Thus, by selectively and sequentially utilizing this comparison feedback technique, at `balance the analog input signal Ea and the comparison voltage Ec will be substantially equal, and thus by sampling the register tlip-ilops A, B, C, D, E and F, a logarithmic digital output number representative of the analog input signal can be obtained as will be described below.

Referring again to FIG. 1 for the principle of operation, a logarithmic base a is chosen and represents the base of the desired logarithm. For example, a could represent the natural log to the base e or the log to the 'base 1t). The output register 11, which will hold the binary number resulting from the conversion process, is shown for representing six bits corresponding to the number 7.785 (Le. 111.111 in binary digital code) and .having its binary point between the ip-flop C and the hip-flop D of the output register 11. Further, it will be observed that the presence of an output digit or a l in the register 11 controls a two position switch which selects either of two signal paths. A multiplication factor of l is selected when the corresponding digit of the bi-s'table fliptlop is in a tl state, and a factor which is an appropriate power of a is selected when the corresponding digit of the bi-stable tlip-llop to which it is coupled is in a 1 state. The power of a controlled by a particular digit where r is the power of 2 represented yby lthat digit in the register. In other words, r designates the position of the digit in any register, relative to the binary point; digits to the left of the point corresponding to values of r equal to 0, l, 2, etc. and digits to the right of the point corresponding to r equal to -l, 2, 3, etc., respectively.

1t can ybe seen that the application of the comparison output voltage Ec and the voltage from the logarithmic digital to analog converter voltage Ea applied to the voltage comparative circuit 13 will produce an output signal indicating whether the input analog voltage Ea exceeds the comparison voltage EC, or vice versa.

Each conversion operation or sampling of the input analog voltage Ea consists of an ordered sequence of in tests where m is the total number of digits in the output register. For the first test all the digits in the register 11 are set in the 0 state except the first bi-stable flip-flop A, which represents the most significant digit. This flipflop A is set to the "1 state. The timing and control circuit 10 performs this function and will be described at a later time with reference to FIG. 3. Due to the bistable tlip-flop A being placed in the l state an output will be applied to the switch 23 so that the a4 multiplication factor will be applied to the reference voltage E0. All the other switches will at the same time connect. the times l" factor in the logarithmic digital to analog convertex' 12. Then, if the decision signal out of the voltage comparator 13 indicates that the analog signal voltage Ea exceeds the comparison voltage Ec, the first digit in the digital output register 11 is permitted to remain at "l" and we then proceed to the second test; if the comparison indicates that E.c is greater than En, the Ibi-stable flip-flop A will be re-set to the "0 state before proceeding to the next test.` The required value for the first digit having thus been determined, the remaining digits of the digital register 11 are maintained at 0, that is fiip-ops C, D, E and F are maintained in the 0 state except that flip-flop B, representing the next most significant digit, is set to a 1." Now, if the decision signal, that is the signal from the voltage comparator 13, indicates that the voltage E, exceeds the comparison voltage Ec, bistable Hip-flop B, that is the second most significant digit, is allowed to remain at "1; if not, the second digit is re-set to 0 before proceeding to the next test. Subsequent tests follow a similar proce-dure, each one determining the value of the most significantV remaining digit. After m tests all the digits will have been determined unambiguously. It is thus seen that the comparison voltage Ec consists of a product of a number of contributions, the magnitude of each contribution being determined by the corresponding digit in the output register 11. Furthermore, it is seen that at balance E=EoaN and therefore N, the number in the digital output register 11, is equal to E.. loge or log, En-log E0, where Eo is the reference signal or voltage whose magnitude determines the scale factor of the conversion. This explanation is intended to cover the main feature of operation of this device and purposely omits such minor points as the correct rounding off of the output number and the provision of sample and hold i v across operational amplifier 120.

circuits for detecting a varying input voltage, all of which are the same as would be applicable to the standard linear A-D converters presently available on the market.

Referring now to FIG. 2, there is shown details of an embodiment of an anti-logarithmic digital to analog converter in schematic form in accordance with the antilogarithmic digital to analog converter of FIG. 1. Reference voltage Eo is applied at one end of the anti-logarithmic digital to analog converter device -to provide a conversion voltage Ec. This device comprises a plurality of operational amplifiers 100, 110, 120, 130, .140 and 150. The operational amplifiers could Ibe of that type described in the book Analog Methods, Second Edition, authored by Karplus and Soroka, published by the McGraw-Hill Book Company in 1959, particularly that described in chapter 2, secs. 2.9-2.15. A plurali-ty of input resistors 101, 111, 121, 131, 141 and 151 -is shown coupled to each of these operat-ional amplifiers referred to above. There is also shown a plurality of feedback resistors coupled across each operational amplifier. For example, operational amplifier is provided with a feedback resistor 102 which is weighted to represent the value of the resistance 101 times a4 and is also provided with a feedback resistor 103 which is equal to the magnitude of resistor 101. By the useof the relay 104, an arm 105 can be moved from a contact 107 coupled to the times 1 path, to contact 106, which is coupled to the a4 multiplication path. Thus, by providing an output on the 1 line from bi-stable flip-flop A, a multiplication factor can be selected in accordance with a number set in the respective fiipflops of the digital register. Operational amplifier 100 is also shown' having multiplication factor resistors 112 and 113 with a relay device 114 for selectively controlling the appropriate multiplication factor in accordance with a signal from bi-stable Hip-flop B. This device operates similarly as described with reference to the multiplication factors coupled across operational amplifier 110.

The third multiplication factor, that is either a or l is provided across operational amplifier by the combination of resistors 122 and 123. By applying an appropriate signal from bi-stable flip-flop C, relay 124 can move arm 125 between contacts 126 and 127, thereby A fourth multiplication factor that is representative of either a'f or l is provided by resistors 13 2 and 133. By appropriately controlling relay 134 with a signal from bi-stable ip-flop D, movable arm 135 can be positioned between the contacts 136 and 137 to selectively choose the required multiplication factor.

A fifth pair of multiplication factors are provided by a resistor 142 representing af and a resistor 143 representing times 1'.` By appropriately operating relay 144 in accordance with a signal provided by bi-stable fiip-flop E, relay arm 145 can be selectively positioned at either contact 146 or 147 to provide the required multiplication factor in the manner described above.

The last multiplication factor for this lparticular six digital system is provided by a resistor 152 representing the multiplication factor ati and a resistor 153 representing times 1 by selectively providing an output signal from bi-stable liip-op F to relay 154, arm 155 can be coupled to either contact 156 or 157 to selectively choose the required multiplication factor. It is thus seen that an input voltage Eo will be selectively operated on by a digital signal in such a manner that a logarithmic digital number can be converted to an analog signal representative of said logarithmic digital number. Therefore, this particular digital-analog conversion device can be utilized either as an element in a logarithmic AD. converter or as an output device for providing a conversion of a digital signal to obtain an analog output signal. It is also seen that any digital number, whether representative of a logarithm or not, can be rconverted to an analog signal representative of the selective multiplication of an input reference signal.

Referring now to FIG. 3, there is shown a logical fiow diagram of the timing and control circuit of this invention in block diagram form. The voltage comparator 13 and the output register 12 comprising flip-Hops 20, 30, 40, 50, 60 and 70 are` also shown in block form. The timing and control circuit referred to as block 10 in FIG. l-comprises a clock circuit for providing timing pulses to initiate operation of this system. This clock is of the Well known pulse type. A plurality of delay line-pulse amplier combinations shown as delay line 200 and pulse amplifier 201, delay line 210 and pulse amplifier 211, delay line 220 and pulse amplifier 221, delay line 230 and pulse amplifier 231, delay line 240 and pulse amplifier 241, and delay line 250 and pulse amplifier 251 are serially ooupled to each other and to the clock pulse circuit 199. This serial combination of delay lines and pulse amplifiers provides sequential and selective actuating pulses which are applied to control the `bi-stable flip-flops of the output register l2. Coupled to the voltage comparator 13 are a plurality of AND gates 202, 212, 222, 232, 242 and 252 for logically gating the result of a comparison between Ea and En to selectively actuate the flip-ops of output register 12. These comparison signals are gated in accordance with pulses obtained from the delay line pulse amplifier serial combination referred to above. There is also shown a plurality of OR circuits 213, 223, 233, 243 and 253, coupled respectively to bi-stable flip-flops 30, 40, 50, 60 and 70. It is noted that bi-stable fiip-op 20 does not have an OR circuit coupled to it inasmuch as it is not required for the logical operation of this system. Referring again to FIG. 3 for the principle of operation, the clock circuit 199 provides a signal which initiates three occurrences. Bi-s-table flip-flop 20 is set in the l state and bi-stable fi'ip-fiops 30, 40, 50, 60 and 70 are placed in the 0 state. Additionally, this signal from the clock circuit 199 is applied to the delay line 200 and thus initiates a signal ow through the delay line and pulse amplifier serial combination.

The setting of bi-stable flip-nop 20 in the l sta-te causes a comparison signal Ec to be provided to the yoltage comparator r13 in accordance with the mode of opr eration described with reference -to FIGS. l and 2. The

voltage comparatorllS then compares the analog input l? signal En with the comparison signal Ec. If Ec is less than En, voltage comparator 13 will not provide an output signal. If EC is greater than En, an output signal will be provided over line m. This output signal is an indication that the generated comparison voltage Ec is greater than Ea. Thus, bi-stable liip-ilop 20 will have to be re-set to the O state. This is accomplished by the simultaneous application of the delayed signal which passes through delay line 200 and pulse amplier 201, and the signal generated from the result of the comparison of E,s and Ea being applied to AND circuit 202. The application of these two signals will cause bi-stable ip-ilop 20 to se set to the state. Additionally, the output from pulse arnplier 201 will cause bi-stable Hip-flop 30 to be placed in the l state in order to generate the second comparison signal in accordance with the operation described with reference to FIGS. l and 2. The remainder of -the operation, that is the remainder of the sequenced comparison tests, is completed in a similar fashion as described with reference to bi-stable ip-tlop 20. This type of control circuit, described above, is typically shown as a block diagram control circuit, page 489,'FIG. ll-8(a) in :the book Digital Computer Components and Circuits, by R. K. Richards, published by D. Van Nostrand Co., Inc., in November of 1957.

Referring now to FIG. 4, there is shown a typical logica-l low-pass all-pass lumped parameter delay line section adapted to pass the clock pulses and Which could be utilized as one of a plurality of sections of thedelay lines 200, 4210, 220, 230, 240 and 250, shown in FIG. 3. The delay line section comprises a plurality of inductances 300, 303 serially coupled and a third inductance 301. coupled at one end to the junction of inductances 300 and 303. Coupled to the other end of inductance 301 is a capacitor 302, and coupled across the serial combination of inductances 300 and 303 is a capacitor 304. Other well known delay line sections could be substituted in place of this delay line section. f

With reference to FIG. 5, a typical delay line pulse amplifier circuit is'shown comprising PNP transistors 400 and 410. This typical pulse amplifier circuit is utilized for rejuvenating the attenuated signal provided from the delay line circuits of FIG. 3. Other types of pulse amplitier circuits for producing this resu'lt are well known in the prior art.

Since many changes could be made in the abovedescribed construction and inany apparently Widely different embodiments of the present invention could be made without departing from the scope thereof, it is maintained that all `matter contained in the above description or shown in `the accompanying drawings should be interpreted as .illustrative and not in a` limiting sense.

What is claimed is:

1. A converter for changing an analog signal representation to a digita-l logarithm representation having a predetermined base, comprising a comparator circuit to compare an analog signal with a generated comparison signal, a control circuit operating lin response to said comparison signal, said control circuit providing Ia pluralty of sequential actuating signals, a register having a plurality of .storage devices each representing a value of two to la different power and being responsive to said actuating signals for providing a plurality of selection signals, and an anti-logarithmic digital to analog con- ,verter responsive to said selection signals including a plurality of multiplier means for selectively multiplying a reference signal by a plurality of successive weighted constants to generate said comparison signal, each of said multiplier means being coupled to a different one of said storage devices for multiplying, in response thereto, by a weighted constant having a value of said base to a power equal to the value represented by the coupled storage device.

2. An anti-logarithmic digital to analog conversion dcvice comprising means for storing a number represented by a binary digital word and in accordance with said binary word providing a plurality of selection signals, and means for multiplying a reference signal by a serially coupled plurality of multiplication factors .in accordance with the magnitude of the number represented by said binary digital word comprising a plurality of means each including at least two multiplier means with one of said multiplier means operative to multiply said reference signal by a factor equal to a predetermined Ilogarithm base to a power of two to a power and a second one of said multiplier means operative to multiply said reference signal by a factor of one, and a switching means responsive to one of said selection signals for selectin-g one of said at least two multiplier means.

3. A system for changing an analog signal representation to a digital logarithm representation having a predetermined base comprising means to receive an analog input signal, means for comparing said input signal with a comparison signal to generate an intermediate signal, a digital register responsive to said intermediate signal for storing a digital number and in response thereto producing a plurality of selection signals, and means responsive to said selection signals for selectively multiplying a reference signal and a plurality of serially cou-pled weighted constants to generate said comparison signal comprising a plurality of means each including at least two multiplier means with one of said multiplier means operative to multiply said reference signal by a factor equal to said base to a power of two to a power and a second one of said multiplier means operative to multiply said reference signal by a factor of one, and a switching means responsive to one of said selection signals for select-ing one of said at lleast two multiplier means.

4. The invention accord-ing to claim 1 and wherein:

said register is operative to store a binary word having a plurality of digits with each digit being stored in a different storage device.

5. The invention according to claim 1 and wherein:

said register is operative to store a binary word having a plurality of digits with each digit being stored -in a different storage device; and,

said control circuit includes a plurality of delay means serially connected.

6. The invention according to claim 2 and wherein:

said means for storing a number comprises a plurality of flip-Hops, each operative in first and second states and producing a different selection signal in each state of operation.

7. The invention according to claim 3 and wherein:

said digital register comprises a plurality of flip-flops,

each operative in tirst and second states and producing a different selection signal in each state of operation.

Refereuces Cited by the Examiner UNITED STATES PATENTS 2,597,866 5/1952 Gridley 340-347 2,784,396 3/1957` Kaiser et al. 340--347 OTHER REFERENCES Pages 36-40, February l, 1962, Electronics Design. Pages 30-31, October, 1962, IBM Technical Disclosure Bulletin, vol. 5, No. 5.

Nov. 20, 1957, 8 pp., The Multiverter, an Engineering Bulletin published by Packard-Bell Computer Corp.

MAYNARD R. WILBUR, Prima/y Examiner.

MALCOLM A. MORRISON, Examiner.

K. RVSTEVENS, I. F. MILLER, Assistant Examiners. 

1. A CONVERTER FOR CHANGING AN ANALOG SIGNAL REPRESENTATION TO A DIGITAL LOGARITHM REPRESENTATION HAVING A PREDETERMINED BASE, COMPRISING A COMPARATOR CIRCUIT TO COMPARE AN ANALOG SIGNAL WITH A GENERATED COMPARISION SIGNAL, A CONTROL CIRCUIT OPERATING IN RESPONSE TO SAID COMPARISON SIGNAL, SAID CONTROL CIRCUIT PROVIDING A PLURALITY OF SEQUENTIAL ACTUATING SIGNALS, A REGISTER HAVING A PLURALITY OF STORAGE DEVICES EACH REPRESENTING A VALUE OF TWO TO A DIFFERENT POWER AND BEING RESPONSIVE TO SAID ACTUATING SIGNALS FOR PROVIDING A PLURALITY OF SELECTION SIGNALS, AND AN ANTI-LOGARITHMIC DIGITAL TO ANALOG CONVERTER RESPONSIVE TO SAID SELECTION SIGNALS INCLUDING A PLURALITY OF MULTIPLIER MEANS FOR SELECTIVELY MUTIPLYING A REFERENCE SIGNALS BY A PLURALITY OF SUCCESSIVE WEIGHTED CONSTANTS TO GENERATE SAID COMPARISON SIGNAL, EACH OF SAID MULTIPLIER MEANS BEING COUPLED TO A DIFFERENT ONE OF SAID 